an article about who will lead the "system on a chip" market and intellectual property from 1998

System-on-a-chip expectations are too high. Typically 25 percent or less of a single-chip system design is synthesizable logic, and many include mixed-signal sections requiring a great deal of nonreusable, design-specific engineering effort. Further, chips with 1 million gates or more cannot be easily populated with IP blocks averaging from 15,000 to 25,000 gates each that would leave the designer to consider the block-level interconnect for 40 to 60 subsystems, in addition to large blocks of embedded memory or large, fixed cores. The popular market message that customers need only to buy commercial EDA tools, a third-party cell library, and IP blocks, then snap them together like Lego blocks for transmittal to a variety of foundries, is oversimplified at best.